Test on The processor and the instruction cycle

Question 1: In an interactive CPU simulation, the 'Fetch,' 'Decode,' and 'Execute' phases for each instruction are often highlighted or explicitly labeled.

A. Yes

B. No

Explanation: The study materials state that during an interactive simulation of a small CPU, students will observe 'Phase Transitions' where the simulation will often highlight or explicitly label the 'Fetch,' 'Decode,' and 'Execute' phases for each instruction, reinforcing the cyclical nature of CPU operation.

Question 2: During an interactive simulation of a CPU's instruction cycle, what specific observation can a student make regarding the Instruction Register (IR)?

A. Its binary representation will appear in the IR as each instruction is fetched.

B. It will hold the memory address of the next instruction to be fetched.

C. It will temporarily hold the data being read from or written to memory.

D. It will store operands for arithmetic and logic operations.

Explanation: As stated in the study materials under 'Observing the Instruction Cycle in a Simulation,' specifically regarding 'Instruction Register (IR) Content,' it is observed that 'As each instruction is fetched, its binary representation will appear in the IR, illustrating how the CPU loads the current instruction for processing.'

Question 3: During the execute stage of the STORE instruction at memory address 0002, data is read from memory into the MDR.

A. Yes

B. No

Explanation: In Cycle 3, for the STORE instruction at memory address 0002, the execute stage involves sending the ACC's content (8) to the MDR, then sending the memory address 1010 to the MAR, and finally sending a write signal to memory to store the MDR's content (8) at address 1010. This is a memory write operation, not a memory read operation into the MDR during this specific execute stage.

Question 4: During the fetch stage of each instruction cycle, the Program Counter (PC) increments its value immediately after its current value is transferred to the Memory Address Register (MAR) and the instruction is retrieved from memory.

A. Yes

B. No

Explanation: In every instruction cycle's Fetch stage, the PC's value is first transferred to the MAR, then the instruction is moved from memory to the IR, and finally, the PC increments. For example, in Cycle 1, PC (0000) goes to MAR, then PC increments to 0001. This pattern repeats in subsequent cycles like Cycle 2 (PC 0001 to MAR, then increments to 0002) and Cycle 3 (PC 0002 to MAR, then increments to 0003).

Question 5: Based on the provided memory layout and program trace, which statement accurately describes the storage of instructions and data?

A. Instructions are stored in memory addresses from `0000` to `0003`, while data values are stored starting from memory address `1000`.

B. All program instructions and data values are stored sequentially in memory, starting from address `0000`.

C. The operand of an instruction always refers to an instruction address, not a data address.

D. Memory address `1010` initially holds the value 8 before the program begins execution.

Explanation: The memory layout shows instructions (LOAD, ADD, STORE, HALT) residing at addresses `0000`, `0001`, `0002`, and `0003`. Data values (5, 3) are explicitly shown at addresses `1000` and `1001`, with `1010` initially being empty. Therefore, instructions and data are stored in distinct memory address ranges in this example. The operand of instructions like LOAD, ADD, and STORE refers to data memory addresses. Memory address `1010` is initially empty and only receives the value 8 during the execution of the STORE instruction in Cycle 3.