Flashcards on The processor and the instruction cycle

The Processor and the Instruction Cycle Explained (CPU Basics)

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What is the repetitive process that enables the CPU to process information and execute programs?

The instruction cycle, also known as the fetch-decode-execute cycle.

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CPU Instruction Cycle

34 cards

Card 1

Question: What is the repetitive process that enables the CPU to process information and execute programs?

Answer: The instruction cycle, also known as the fetch-decode-execute cycle.

Card 2

Question: What is the purpose of registers within the CPU?

Answer: Registers are small, high-speed storage areas within the CPU that hold data and instructions temporarily during processing, offering faster access tha

Card 3

Question: Which CPU register holds the memory address of the *next* instruction to be fetched?

Answer: The Program Counter (PC).

Card 4

Question: What happens to the Program Counter (PC) after each instruction fetch?

Answer: It is automatically incremented to ensure sequential program execution.

Card 5

Question: Where is an instruction temporarily stored after it is fetched from memory for decoding and execution?

Answer: The Instruction Register (IR).

Card 6

Question: Which register holds the memory address that the CPU wants to read from or write to?

Answer: The Memory Address Register (MAR).

Card 7

Question: Which register temporarily holds the data being read from or written to a memory location?

Answer: The Memory Data Register (MDR).

Card 8

Question: What is the function of the Accumulator (ACC) or General-Purpose Registers?

Answer: They are used to store operands for arithmetic and logic operations and the results of those operations.

Card 9

Question: What CPU component performs all arithmetic and logical operations?

Answer: The Arithmetic Logic Unit (ALU).

Card 10

Question: What is the role of the Control Unit (CU) in the CPU instruction cycle?

Answer: It orchestrates the entire instruction cycle, interprets instructions, generates control signals, and manages data flow within the CPU and between the