Test on MIPS Instruction Set Architecture Fundamentals

Question 1: MIPS assembly language includes direct conditional branch instructions such as `blt` for branching if less than, allowing for a single instruction to handle such comparisons and branches.

A. Ano

B. Ne

Explanation: MIPS intentionally does not include direct conditional branch instructions like `blt` or `bge`. The study materials explain that hardware for comparisons like less than (<) or greater than or equal to (≥) is slower than for equality (=) or inequality (≠). Combining these complex comparisons with a branch would require more work per instruction, leading to a slower clock for all instructions. Instead, MIPS uses a design compromise where less common conditions are handled by combining a `slt` (set if less than) instruction with a `beq` or `bne` instruction.

Question 2: Which statement accurately describes the MIPS addressing modes for branches and jumps as presented in the study materials?

A. Branch instructions use PC-relative addressing with a 16-bit offset, where the target address is calculated as PC + (offset × 4), after PC has already been incremented by 4. Jump instructions use (pseudo)direct addressing, concatenating the upper 4 bits of the PC with the 26-bit address field multiplied by 4.

B. Both branch and jump instructions use PC-relative addressing, where the target address is always calculated relative to the current Program Counter (PC) value.

C. Branch instructions use (pseudo)direct jump addressing with a 26-bit address field, while jump instructions use PC-relative addressing with a 16-bit offset.

D. The target address for both branch and jump instructions is simply the 32-bit immediate value provided directly within the instruction.

Explanation: According to the study materials, branch instructions (like beq, bne) use PC-relative addressing. The target address is calculated as PC + (offset × 4), and the PC is already incremented by 4 by this time, with the offset being 16 bits. Jump instructions (like j, jal) use (pseudo)direct jump addressing, where the target address is formed by concatenating the upper 4 bits of the PC with the 26-bit address field from the instruction, then multiplying by 4. This allows jump targets to be anywhere in the text segment, while branch targets are typically near. Option 1 incorrectly states both use PC-relative addressing. Option 2 swaps the addressing modes. Option 3 describes 32-bit constants (lui/ori) rather than branch/jump addressing.

Question 3: Unsigned binary integers, when represented using n bits, have a range that includes negative values.

A. Ano

B. Ne

Explanation: According to the study materials, the range for an n-bit unsigned binary number is from 0 to +2^n – 1. This range only includes non-negative numbers, meaning no negative values can be represented.

Question 4: Which of the following is a field found in a MIPS R-format instruction?

A. constant

B. rs

C. address

D. offset

Explanation: The study materials list 'op', 'rs', 'rt', 'rd', 'shamt', and 'funct' as fields in a MIPS R-format instruction. 'constant', 'address', and 'offset' are associated with I-format instructions or their components.

Question 5: The complex instruction set of IA-32 makes its implementation difficult.

A. Ano

B. Ne

Explanation: Implementing IA-32 is made difficult by its complex instruction set, as stated in the study materials.