Summary of MIPS Instruction Set Architecture Fundamentals
MIPS Instruction Set Architecture Fundamentals: A Guide
Introduction
MIPS assembly is a concise, regular instruction set used to express low-level operations for processor cores. This guide focuses on the practical aspects of writing and understanding MIPS code used frequently in systems programming and embedded software. You will learn addressing modes, common instructions for data movement and logic, string and array handling patterns, branching and jumps, synchronization primitives, and examples that demonstrate how to implement common tasks in MIPS.
Definition: MIPS is a reduced-instruction-set computer (RISC) architecture with a regular instruction format, a fixed-size register file, and load/store memory model.
Registers and Data Types
- MIPS uses 32 registers, each 32 bits wide, named $0..$31 and by assembler names such as $t0-$t9 (temporaries) and $s0-$s7 (saved registers).
- Memory is byte-addressable; a word = 4 bytes. MIPS is typically big-endian in presentation materials (most-significant byte at the lowest address).
Definition: Byte-addressable memory means each address refers to an 8-bit byte.
Important register usage conventions
- $zero ($0): always reads as 0
- $a0-$a3: argument registers for procedures
- $v0-$v1: values returned from procedures
- $ra: return address for procedure calls
Basic Instruction Categories
- Arithmetic: add, sub, addi (immediate)
- Logical and Bitwise: and, or, nor, sll, srl
- Memory access: lw, sw, lb, lbu, lh, lhu, sb, sh
- Control flow: beq, bne, j, jal
- Comparison: slt, slti
- Atomic synchronization: ll, sc
Definition: Load/store architecture means arithmetic instructions operate only on registers; memory is accessed explicitly via load and store instructions.
Immediate and 32-bit Constants
- Most immediates fit in 16 bits; use addi for small constants.
- For a 32-bit constant, use lui to load upper 16 bits and then ori (or) to set low 16 bits.
Example: load 32-bit constant into $s0
$$\text{lui }$s0, 61$$ $$\text{ori }$s0, $s0, 2304$$
This sequence places the 16-bit value 61 in the high half and 2304 in the low half of $s0.
Memory Access: Bytes and Halfwords
- lb rt, offset(rs): load signed byte and sign-extend to 32 bits
- lbu rt, offset(rs): load unsigned byte and zero-extend to 32 bits
- lh rt, offset(rs): load signed halfword and sign-extend
- lhu rt, offset(rs): load unsigned halfword and zero-extend
- sb rt, offset(rs): store rightmost byte of register to memory
- sh rt, offset(rs): store rightmost 16 bits (halfword)
Definition: Sign extension copies the sign bit (most-significant bit) into upper bits when converting a smaller signed quantity to a larger width.
Example: Copying a Null-Terminated String (strcpy)
C prototype (naïve):
void strcpy(char x[], char y[]) {
int i;
i = 0;
while ((x[i] = y[i]) != '\0')
i += 1;
}
MIPS implementation notes:
- $a0 contains address of destination x
- $a1 contains address of source y
- $s0 used as index i (saved register)
- Use lbu to read bytes and sb to write bytes
- Use loop with beq to test for the terminating zero
MIPS sequence (conceptual flow):
- Save $s0 on stack
- Initialize $s0 = 0
- Loop:
- compute address of y[i] as $a1 + $s0
- lbu $t2, 0($t1)
- compute address of x[i] as $a0 + $s0
- sb $t2, 0($t3)
- if $t2 == 0, exit
- increment $s0 and repeat
- Restore $s0 and return
This pattern demonstrates byte-level memory operations and index-based address computation.
Branching and Jumping
- Branch instructions (beq, bne) include a 16-bit signed offset that is PC-relative. The target address is computed as PC + 4 + (offset << 2).
- Jump instructions (j, jal) supply a 26-bit target field; the real target is formed by combining the top bits of PC with the 26-bit field shifted left by 2: PC_{31..28} : (
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MIPS Assembly Essentials
Klíčové pojmy: MIPS uses 32 registers; $zero is always 0, Use lb/lbu, lh/lhu, sb/sh for byte/halfword load/stores; lbu/lhu zero-extend, Load 32-bit constants with lui then ori, Branch targets are PC-relative (16-bit offset); jumps use 26-bit field and PC high bits, Use slt/slti plus beq/bne to implement relational branches like blt, String copy: use lbu to read bytes, sb to write, loop until '\0', ll and sc implement atomic read-modify-write; loop on sc failure, Pointer iteration avoids repeated multiply for sequential array traversal, Save/restore callee-saved registers and $ra on stack in procedures, Use sll to multiply by powers of two (e.g., index * 4), Assembler rewrites far branches into conditional+jump sequences, Prefer immediates (addi) for small constants to avoid loads