Test on Digital Electronics: Concepts and Applications

Question 1: The provided VHDL architecture body for a 4-to-1 multiplexer (Listing A.10) defines its functionality using a process statement.

A. Yes

B. No

Explanation: Listing A.10 defines the 4-to-1 multiplexer using a conditional signal assignment (`y <= a when sel = "00" else ...`), which is not a process statement. The solution describes it as a 'behavioral' architecture, but the implementation itself does not use a VHDL 'process'.

Question 2: According to the provided study materials, which term is added algebraically to mask a static-0 hazard in the logic function f(c, b, a) = (ca · a) + ba?

A. ca

B. ba

C. c + b

D. c + a

Explanation: The solution to Exercise 4.4, which asks to mask a static-0 hazard algebraically in the logic function f(c, b, a) = (ca · a) + ba, shows that the free function is f_free(c, b, a) = [(ca · a) + ba] · (c + b). This indicates that the term (c + b) is added algebraically to mask the static-0 hazard.

Question 3: A basic NAND gate S-R latch circuit is characterized by providing feedback from both of its outputs back to its opposing inputs.

A. Yes

B. No

Explanation: The study materials state: 'A basic NAND gate S-R latch circuit provides feedback from both of its outputs back to its opposing inputs and is commonly used in memory circuits to store a single data bit.'

Question 4: What is the primary method for modifying a basic S-R latch to create a Gated S-R latch, incorporating an enable input?

A. By connecting a 2-input NOR gate in parallel with each input terminal of the S-R latch.

B. By adding an inverter to make the R value complement to the S value.

C. By connecting a 2-input NAND gate in series with each input terminal of the S-R latch.

D. By adding a second gated S-R latch to its output activated on the complementary enable signal.

Explanation: A Gated S-R latch is created by connecting a 2-input NAND gate in series with each input terminal of the S-R latch. This adds an extra control input called an enable input (en).

Question 5: The maximum clock frequency of a 3-bit asynchronous counter with a propagation delay of 17 ns per flip-flop and a set-up time of 2 ns is calculated by dividing 1 by the sum of 17 ns and 2 ns.

A. Yes

B. No

Explanation: For a 3-bit asynchronous counter, the total propagation delay of the flip-flops is equal to 3 multiplied by the propagation delay of a single flip-flop. Therefore, the maximum clock frequency is calculated by dividing 1 by the sum of (3 17 ns) and 2 ns, not just 17 ns and 2 ns.